This disclosure relates generally to nonvolatile memory devices. More particularly, the present disclosure relates to nitride flash memory devices and methods for manufacture thereof.
Nonvolatile memory devices may have various structural designs. FIG. 1 shows an example of a nonvolatile memory cell that is implemented in and on a substrate. A memory cell may comprise source and drain regions 10, as well as a channel 20 disposed between the source and drain regions. Overlying channel is a charge-trapping or ONO structure 25, which may comprise a charge-trapping nitride layer 30 (e.g. silicon nitride) disposed between two oxide layers 40 (e.g. silicon oxide). Each memory cell may further comprise a gate electrode 50 that overlies the charge trapping structure 25. The charge-trapping structure 25 and the gate electrode 50 may be isolated from other structures on the substrate, such as source and drain contacts by spacers 60 shown in FIG. 1. By properly manipulating the relative voltages among source region, drain region and gate, it is possible to erase, store (or program) and read two separate bits of information in each memory cell.
A number of methods for forming the oxide and nitride layers of a non-volatile memory device are known. For example, U.S. Pat. No. 6,362,051 entitled “Method of Forming ONO Flash Memory Devices Using Low Energy Nitrogen Implantation,” by Yang et al., discloses a method for fabricating a non-volatile memory device having a layer that contains a silicon nitride layer sandwiched between two silicon oxide layers.
In another example, U.S. Pat. No. 6,620,742 entitled “In-Situ Use of dichloroethene and NH3 in an H2O Steam Based Oxidation System to Prevent a Source of Chlorine,” by Powell, discloses a method for forming a semiconductor dielectric in the presence of strengthening and gettering agents. The method includes the simultaneous use of gaseous strengthening and gettering agents on a semiconductor dielectric, for example NH3 in an H2O Steam Based Oxidation System.
In yet another example, U.S. Pat. No. 6,638,877, entitled “Ultra-Thin SiO2 Using N2O as the Oxidant,” by Rotondaro, discloses a structure and method of forming an ultra-thin oxide structure. In particular, an oxide layer is grown over a substrate using N2O and with the addition of hydrogen.
However, a number of concerns exist regarding known non-volatile memory devices and methods for manufacturing. For example, increases in interface trap densities (Dit) in a memory device may cause severe degradation of the device performance and adversely affect the operating life. Interface trap generation may occur as a device is cycled (continuous programming and erasing) causing current-voltage swing degradation and threshold voltage (Vt) shift. FIG. 2 shows the effect of write/erase cycles on I-V swing (Sw), interface trap charge (Qit), and Vt loss.
In one example, because of the interface trapped charges at the oxide/silicon interface, it is possible the actual amount of charges programmed into the charge-trapping structure 25 may be reduced by Qit. Therefore, only (PV-EV)*Cono)-Qit is programmed into the ONO structure, wherein PV stands for programming voltage, EV stands for erasing verify voltage, and Cono stands for the capacitance of the ONO structure. In some cases, high temperature baking may anneal the trap charge Qit, leading to equivalent Vt loss, which may be in the amount of Qit/Cono. As an example, the percentage of ONO charge loss caused by Qit is (Qit/(Cono*(PV-EV)))*100.
Interface traps may also be present in a fresh device. The amount of interface traps can cause a recombination current in charge pumping measurement, and the amount of recombination current is proportional to the amount of interface traps. FIG. 3 plots the change in charge pumping current (Icp), which is the recombination current from the interface traps, over the number of program/erase cycles of a non-volatile memory device. The experimental data shown in FIG. 3 shows that a large initial Icp indicated a small Icp increase as a non-volatile memory device was cycled.
While high temperature baking may anneal interface traps, and annealing of interface traps may also contribute to Vt loss, which may result in data retention problems in a high temperature environment. FIG. 4 plots Vt versus time for a fresh device and a device that underwent 100,000 cycles at a temperature of 250° C. Experimental data showed that Vt loss was greater for the cycled device than for a fresh device in high temperatures.
Thus, a fresh non-volatile memory device with a large Dit is subject to a slower growth rate of Dit during cycling compared with a fresh device with a small Dit. Also, a fresh device with a low quality of bottom oxide (BOX) could not properly retain data in high temperature environments. Accordingly, it is desirable to have a non-volatile memory device with a large Dit, i.e., low quality interface, but with a high quality BOX.